charbel.synthesis — com.github.m1kal/charbel 0.1.0

build clj

(build {:keys [name config ports body]})

Generate SystemVerilog code based on the output of module function.

build-body clj

(build-body body clocks)

build-clock-inputs clj

(build-clock-inputs clocks)

build-element clj multimethod

build-parameter-list clj

(build-parameter-list parameters)

build-ports clj

(build-ports ports)

declare-signals clj

(declare-signals clocks ports body)

port clj

(port [dir name width])

signal-width clj

(signal-width width)