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charbel.core

buildclj

(build input)

Generate SystemVerilog code based on the output of module function.

Generate SystemVerilog code based on the output of module function.
sourceraw docstring

modulecljmacro

(module & args)

Create intermediate representation from input. See README for syntax and examples.

Create intermediate representation from input. See README for syntax and examples.
sourceraw docstring

module-from-stringclj

(module-from-string input)
source

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