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charbel.core


buildclj/s

(build input)
(build input postprocess)

Generate SystemVerilog code based on the output of module function.

Generate SystemVerilog code based on the output of module function.
sourceraw docstring

moduleclj/smacro

(module & args)

Create intermediate representation from input. See README for syntax and examples.

Create intermediate representation from input. See README for syntax and examples.
sourceraw docstring

module-from-stringclj/s

(module-from-string input)

Create intermediate representation from input string. See README for syntax and examples.

Create intermediate representation from input string. See README for syntax and examples.
sourceraw docstring

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